The present invention relates to a clock generator in a semiconductor integrated circuit including a plurality of circuits that operate in synchronization with clock signals of different frequencies.
With reduction in the design rules for semiconductor integrated circuit fabrication processes, the number of transistors that can be integrated together on a single chip has been increasing dramatically. This enables the circuit to be multifunctional, thereby reducing the number of components therein and hence the costs thereof. That is, in order to reduce the number of design processes, existing design circuits are remounted. And circuits that need to operate at a specific frequency in conformity with a unified standard are mounted. Furthermore, it is necessary to realize a semiconductor integrated circuit on which circuits operating at various frequencies are mounted, for the purposes of lowering power consumption by lower speed operation. Also, in circuits which send and receive data asynchronously, it is difficult to cover all states by performing operation inspection. In addition, redundant cycles are often needed in order to satisfy functional specifications, which causes decline in function.
For these reasons, it is necessary to realize a semiconductor integrated circuit having mounted thereon circuits operating according to a clock signal of a certain frequency together with circuits operating according to a clock signal obtained by dividing the certain frequency of the former clock signal (hereinafter referred to as a “frequency-divided clock signal”). However, a skew is generated between the reference clock signal and the frequency-divided clock signal, because those clock signals are transmitted through different paths and the like. The occurrence of a skew may cause the semiconductor integrated circuit to malfunction.
As a technique for suppressing skews among flip-flops that are disposed in the end portion in a semiconductor integrated circuit and operate at a single frequency, a technique has been proposed in which the same interconnects and the same transistor structures are formed in the clock transmission paths from the clock source to the flip-flops disposed in the end portion (see Japanese Laid-Open Publication No. 7-321208, for example).
Nevertheless, as the design rules for semiconductor integrated circuit fabrication processes have been reduced, variation in the amount of delay caused by crosstalk, voltage drop, and variation in the chip, such as process variation, has been increasing. Therefore, even if the conventional technique is applied to a semiconductor integrated circuit on which circuit operating at various frequencies are mounted, a skew occurring between a reference clock signal and a frequency-divided clock signal cannot be sufficiently suppressed just by forming the same circuit structures, and thus the problem that timing convergence is significantly worsened remains unsolved.